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nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 1 description the mitsubishi m6mgb/t166s4bwg is a stacked chip scale package (s-csp) that contents 16m-bits flash memory and 4m-bits static ram in a 72-pin s-csp. 16m-bits flash memory is a 1,048,576 words, 3.3v-only, and high performance non-volatile memory fabricated by cmos technology for the peripheral circuit and dinor(divided bit-line nor) architecture for the memory cell. 4m-bits sram is a 262,144words unsynchronous sram fabricated by silicon-gate cmos technology. m6mgb/t166s4bwg is suitable for the application of the mobile-communication-system to reduce both the mount space and weight . ? access time flash memory 90ns (max.) sram 85ns (max.) ? supply voltage vcc=2.7 ~ 3.6v ? ambient temperature i version ta=-40 ~ 85 c ? package : 72-pin s-csp , 0.8mm ball pitch application features mobile communication products pin configuration (top view) f-vcc :vcc for flash f-gnd :gnd for flash s-vcc :vcc for sram a0-a16 :flash/sram f-a17-f-a19 :address for flash s-ce1# :sram chip enable 1 f-we# :flash write enable dq0-dq15 :flash/sram f-wp# :flash write protect f-rp# :flash reset power down s-ce2 :sram chip enable 2 f-ry/by# :flash ready /busy f-oe# :flash output enable nc:non connection 11.0 mm s-lb# :sram lower byte 8.0 mm 12345678 a b c d e f g h i j k l nc nc nc a5 a4 a0 f-ce# du nc nc a7 a6 a3 a1 a2 f-a17 f-a18 nc dq9 dq8 dq0 nc f-wp# f-a19 dq11 du dq10 gnd s-vcc du du dq4 f-vcc f-we# f-rp# dq6 dq5 a10 a9 nc nc nc a11 a15 a14 nc nc nc f-oe# f- ry/by# dq13 s-we# dq14 f-gnd gnd :flash/sram common gnd common address common data i/o s-oe# :sram output enable s-we# :sram write enable index (laser marking) f-gnd ce1# s- s-lb# s-ub# s-oe# dq1 dq2 dq3 dq12 ce2 s- s-a17 du a16 a13 a12 a8 dq15 dq7 s-a17 :address for sram f-ce# :flash chip enable s-ub# :sram upper byte du:don't use (note: should be open)
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 2 block diagram multiplexer input/output buffers dq 15 dq 14 dq 13 dq 12 dq 2 dq 1 dq 0 dq 3 wsm 16mb flash memory x-decoder y-decoder y-gate / sense amp. f-ce# f-oe# f-we# f-vcc f-gnd/gnd f-wp# f-rp# cui status / id register 128 word page buffer main block 32kw f-ry/by# flash ready/busy output f-a 18 f-a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address inputs flash chip enable input flash output enable input flash write enable input flash write protect input flash reset/power down input main block 32kw bank(ii) 28 parameter block5 16kw parameter block6 16kw boot block 16kw parameter block3 16kw parameter block4 16kw parameter block1 16kw parameter block2 16kw bank(i) parameter block7 16kw f-a 19 data inputs/outputs wsm 4mb sram s-ce1# s-we# s-oe# s-ce2 s-lb# s-ub# address input buffer row decoder s-a 17 262144 word x 16 bits clock generator sense amp. dq 7 dq 0 dq 15 dq 8 s-vcc gnd output buffer datainput buffer datainput buffer output buffer sense amp. a 0 a 1 a 16
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 3 description the flash memory of m6mgb/t166s4bwg is 3.3v-only high speed 16,777,216-bit cmos boot block flash memories with alternating bgo (back ground operation) feature. the bgo feature of the device allows program or erase operations to be performed in one ba nk while the device simultaneously allows read operations to be performed on the other bank. this bgo feature is suitable for mobi le and personal computing, and communication products. the flash memory of m6mgb/t166s4bwg is fabricated by cmos technology for the peripheral circuits and dinor(divided bit line nor) architecture for the memory cells. features boot block m6mgb166s4bwg bottom boot M6MGT166S4BWG top boot other functions soft ware command control selective block lock erase suspend/resume program suspend/resume status register read alternating back ground program/erase operation between bank(i) and bank(ii) auto power down mode organization 1048,576 word x 16bit supply voltage ................................ v cc = 2.7~3.6v access time 90ns (max.) power dissipation read 54 mw (max. at 5mhz) (after automatic power down) 0.33 m w (typ.) program/erase 126 mw (max.) standby 0.33 m w (typ.) deep power down mode 0.33 m w (typ.) auto program for bank(i) program time 4ms (typ.) program unit (byte program) 1word (page program) 128word auto program for bank(ii) program time 4ms (typ.) program unit 128word auto erase erase time 40 ms (typ.) erase unit bank(i) boot block 16kword x 1 parameter block 16kword x 7 bank(ii) main block 32kword x 28 program/erase cycles 100kcycles ................................. ................................. ................................. ............................. ....................... .............................. ................................. ..................... .............. ...................... ......................................... ................................. ........................ ........................ ......................... ......................... ................................. ................................. ................................. .......... 1. flash memory
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg function deep power-down when f-rp# is at vil, the device is in the deep powerdown mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high-impedance(high-z) state. after return from powerdown, the cui is reset to read array , and the status register is cleared to value 80h. during block erase or program modes, f-rp# low will abort either operation. memory array data of the block being altered become invalid. the flash memory of m6mgb/t166s4bwg includes on-chip program/erase control circuitry. the write state machine (wsm) controls block erase and byte/page program operations. operational modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep powerdown mode is enabled when the f-rp# pin is at gnd, minimizing power consumption. read the flash memory of m6mgb/t166s4bwg has three read modes, which accesses to the memory array, the device identifier and the status register. the appropriate read command are required to be written to the cui. upon initial device powerup or after exit from deep powerdown, the flash memory automatically resets to read array mode. in the read array mode, low level input to f-ce# and f-oe#, high level input to f-we# and f-rp#, and address signals to the address inputs (f-a19-f-a17,a16-a0) output the data of the addressed location to the data input/output ( d15-d0). write writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing f-we# to low level, while f-ce# is at low level and f-oe# is at high level. address and data are latched on the earlier rising edge of f-we# and f-ce#. standard micro-processor write timings are used. standby when f-ce# is at vih, the device is in the standby mode and its power consumption is reduced. data input/output are in a high-impedance(high-z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. alternating background operation (bgo) the flash memory of m6mgb/t166s4bwg allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. read array operation with the other bank in bgo is performed by changing the bank address without any additional command. when the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. the access time with bgo is the same as the normal read operation. output disable when f-oe# is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state. automatic power-down (apd) the automatic power-down minimizes the power consumption during read mode. the device automatically turns to this mode when any addresses or f-ce# isn't changed more than 200ns after the last alternation. the power consumption becomes the same as the stand-by mode. while in this mode, the output data is latched and can be read out. new data is read out correctly when addresses are changed. 4
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg software command definitions the device operations are selected by writing specific software command into the command user interface. read array command (ffh) the device is in read array mode on initial device power up and after exit from deep powerdown, or by writing ffh to the command user interface. after starting the internal operation the device is set to the read status register mode automatically. read device identifier command (90h) it can normally read device identifier codes when read device identifier code command(90h) is written to the command latch. following the command write, the manufacturer code and the device code can be read from address 00000h and 00001h, respectively. read status register command (70h) the status register is read after writing the read status register command of 70h to the command user interface. also, after starting the internal operation the device is set to the read status register mode automatically. the contents of status register are latched on the later falling edge of f-oe# or f-ce#. so f-ce# or f-oe# must be toggled every status read. clear status register command (50h) the erase status, program status and block status bits are set to "1"s by the write state machine and can only be reset by the clear status register command of 50h. these bits indicates various failure conditions. block erase / confirm command (20h/d0h) automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation. program commands a)word program (40h) word program is executed by a two-command sequence. the word program setup command of 40h is written to the command interface, followed by a second write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. the word program command is valid for only bank(i). data protection the flash memory of m6mgb/t166s4bwg provides selectable block locking of memory blocks. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the flash memory has a master write protect pin (f-wp#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when f-wp# is low. when f-wp# is high, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. see the block locking table on p.9 for details. power supply voltage when the power supply voltage (f-vcc) is less than v lko, low v cc lock-out voltage, the device is set to the read-only mode. regarding dc electrical characteristics of v lko, see p.10. a delay time of 2 m s is required before any device operation is initiated. the delay time is measured from the time f-vcc reaches f-vccmin (2.7v). during power up, f-rp#=gnd is recommended. falling in busy status is not recommended for possibility of damaging the device. memory organization the flash memory of m6mgb/t166s4bwg has one 16kword boot block, seven 16kword parameter blocks, for bank(i) and twenty-eight 32kword main blocks for bank(ii). a block is erased independently of other blocks in the array. suspend/resume command (b0h/d0h) writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the bank address is required when writing the suspend/resume command. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes. 5 b)page program for data blocks (41h) page program for bank(i) and bank(ii) allows fast programming of 128words of data. writing of 41h initiates the page program operation for the data area. from 2nd cycle to 129th cycle, write data must be serially inputted. address a6-a0 have to be incremented from 00h to 7fh. after completion of data loading, the wsm controls the program pulse application and verify operation. c)single data load to page buffer (74h) / page buffer to flash (0eh/d0h) single data load to the page buffer is performed by writing 74h followed by a second write specifying the column address and data. distinct data up to 128word can be loaded to the page buffer by this two-command sequence. on the other hand, all of the loaded data to the page buffer is programed simultaneously by writing page buffer to flash command of 0eh followed by the confirm command of d0h. after completion of programing the data on the page buffer is cleared automatically. this command is valid for only bank(i) alike word program. clear page buffer command (55h) loaded data to the page buffer is cleared by writing the clear page buffer command of 55h followed by the confirm command of d0h. this command is valid for clearing data loaded by single data load to page buffer command.
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 6 bank(i) bank(ii) 16kword boot block 35 16kword parameter block 34 32kword main block 27 32kword main block 26 32kword main block 25 32kword main block 24 32kword main block 23 32kword main block 22 32kword main block 21 32kword main block 20 32kword main block 19 32kword main block 18 32kword main block 17 32kword main block 16 32kword main block 15 32kword main block 14 32kword main block 13 32kword main block 12 32kword main block 11 32kword main block 10 32kword main block 9 32kword main block 8 32kword main block 7 32kword main block 6 32kword main block 5 32kword main block 4 32kword main block 3 32kword main block 2 32kword main block 1 32kword main block 0 16kword parameter block 33 16kword parameter block 32 16kword parameter block 31 16kword parameter block 30 16kword parameter block 29 16kword parameter block 28 memory organization f-a 19 -f-a 17 ,a 16 -a 0 (word mode) flash memory of m6mgb166s4bwg memory map 32kword main block 35 32kword main block 34 32kword main block 33 32kword main block 32 32kword main block 31 32kword main block 30 32kword main block 29 32kword main block 28 32kword main block 27 32kword main block 26 32kword main block 25 32kword main block 24 32kword main block 23 32kword main block 22 bank(ii) 32kword main block 21 32kword main block 20 32kword main block 19 32kword main block 18 32kword main block 17 32kword main block 16 32kword main block 15 32kword main block 14 32kword main block 13 32kword main block 12 32kword main block 11 32kword main block 10 32kword main block 9 32kword main block 8 bank(i) 16kword parameter block 1 16kword boot block 0 16kword parameter block 2 16kword parameter block 3 16kword parameter block 4 16kword parameter block 5 16kword parameter block 6 16kword parameter block 7 f8000h-fffffh f0000h-f7fffh e8000h-effffh e0000h-e7fffh d8000h-dffffh d0000h-d7fffh c8000h-cffffh c0000h-c7fffh b8000h-bffffh b0000h-b7fffh a8000h-affffh a0000h-a7fffh 98000h-9ffffh 90000h-97fffh 00000h-03fffh 18000h-1bfffh 14000h-17fffh 10000h-13fffh 0c000h-0ffffh 08000h-0bfffh 04000h-07fffh 1c000h-1ffffh 20000h-27fffh 28000h-2ffffh 30000h-37fffh 38000h-3ffffh 40000h-47fffh 48000h-4ffffh 50000h-57fffh 58000h-5ffffh 60000h-67fffh 68000h-6ffffh 70000h-77fffh 78000h-7ffffh 80000h-87fffh 88000h-8ffffh fc000h-fffffh f8000h-fbfffh f4000h-f7fffh f0000h-f3fffh ec000h-effffh e8000h-ebfffh e4000h-e7fffh e0000h-e3fffh d8000h-dffffh d0000h-d7fffh c8000h-cffffh c0000h-c7fffh b8000h-bffffh b0000h-b7fffh 00000h-07fffh 30000h-37fffh 28000h-2ffffh 20000h-27fffh 18000h-1ffffh 10000h-17fffh 08000h-0ffffh 38000h-3ffffh 40000h-47fffh 48000h-4ffffh 50000h-57fffh 58000h-5ffffh 60000h-67fffh 68000h-6ffffh 70000h-77fffh 78000h-7ffffh 80000h-87fffh 88000h-8ffffh 90000h-97fffh 98000h-9ffffh a0000h-a7fffh a8000h-affffh f-a 19 -f-a 17 ,a 16 -a 0 (word mode) flash memory of M6MGT166S4BWG memory map
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 7 1) x at f-ry/by# is v ol or v oh(hi-z) . *the f-ry/by# is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy performing an operation. a pull-up resistor of 10k-100k ohms is required to allow the f-ry/by# signal to transition high indicating a ready wsm condit ion. 2) x can be v ih or v il for control pins. bus operations bus operations for word-wide mode 1) mode array status register identifier code stand by program erase write read pins f-ce# f-oe# f-we# v il v il v il v il v ih v il v il v il v il v il v ih x v ih v ih v ih v ih v ih v ih x v il v il data out status register data identifier code hi-z hi-z command/data in command output disable deep power down others f-rp# v ih v ih v ih v ih v ih v ih v ih f-ry/by# v oh (hi-z) x x x x x x v il v ih x v il x hi-z v ih v il x command dq 0-15 2) v ih lock bit status v il v il v ih lock bit data (dq 6 )x v oh (hi-z) v oh (hi-z)
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg software command definition command list 1) upper byte data (dq8-dq15) is ignored. 2) ia=id code address : a0=vil (manufacturer's code) : a0=vih (device code), id=id code 3) bank = bank address (bank(i) or bank(ii)) : f-a19-f-a17. 4) srd = status register data 5) word program, single data load and page buffer to flash command is valid for only bank(i). 6) wa = write address,wd = write data 7) wa0,wan=write address, wd0,wdn=write data. write address and write data must be provided sequentially from 00h to 7fh for a6-a0. page size is 128wo rd (128word x 16bit). and also f-a19-f-a17,a16-a7(block address, page address) must be valid. 8) wa = write address : upper page address, f-a19-f-a17,a16-a7(block address, page address) must be valid. 9) ba = block address : ba = block address : f-a19-f-a17,a16-a14(bank1) f-a19-f-a17,a16-a15(bank2) 10) dq6 provides block lock status, dq6 = 1 : block unlock, dq6 = 0 : block locked. 8 read array ffh x write 1st bus cycle 2nd bus cycle command device identifier 90h x write id ia read read status register 70h write srd read clear status register 50h x write 2) 4) 2) page program write 41h block erase / confirm suspend resume 7) read lock bit status lock bit program / confirm erase all unlocked blocks write write 20h bank write d0h write b0h bank write 71h x write 9) write write a7h 77h d0h write read ba xd0h d0h dq6 word program 5) write 40h write wd0 write 7) 7) wd 10) single data load to page buffer page buffer to flash write write 74h write wd wa 0eh write d0h 3) clear page buffer 55h x write write x d0h 5) 5) bank bank bank(i) wa bank bank ba bank x wdn write 7) 7) wan wa0 3rd ~129th bus cycles (word mode) 1) 1) address mode data address mode data address mode data (dq15-0) 1) 1) 1) wa 6) 8) 6) (dq15-0) (dq15-0) ba 5) bank(i) 5) bank(i) 5)
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 9 *the f-ry/by# is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy performing an operation. a pull-up resistor of 10k-100k ohms is required to allow the f-ry/by# signal to transition high indicating a ready wsm condit ion. status register status erase status program status definition symbol (dq 5 ) (dq 4 ) write state machine status (dq 7 ) (dq 6 ) (dq 1 ) (dq 0 ) (dq 3 ) (dq 2 ) "1" "0" ready busy suspended operation in progress / completed error successful error successful sr.5 sr.4 sr.7 sr.6 sr.1 sr.0 sr.3 sr.2 block status after program reserved - suspend status error successful - *dq3 indicates the block status after the page programming, word programming and page buffer to flash. when dq3 is "1", the pag e has the over-programed cell . if over-program occurs, the device is block fail. however if dq3 is "1", please try the block erase to the block. the bl ock may revive. reserved reserved -- -- block locking deep power down mode write protection provided locked lock bit (internally) x bank(i) lock bit boot parameter data locked locked locked note bank(ii) v il f-rp# f-wp# x all blocks unlocked 0 1 x locked locked unlocked unlocked unlocked unlocked locked locked locked unlocked unlocked locked v ih v il v ih 1) dq 6 provides lock status of each block after writing the read lock status command (71h). f-wp# pins must not be switched during performing erase / write operations or wsm busy (wsms = 0). 2) erase/write command for locked blocks is aborted. at this time read mode is not array read mode but status read mode and 00b0h is read. please issue clear status register command plus read array command to change the mode from status read mode to array read mode.
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 10 device identifier code the upper data(d 15-8) is "0". code manufacturer code pins hex. data 1ch dq 0 0 a 0 v il dq 1 0 dq 2 1 dq 3 1 dq 4 1 dq 5 dq 6 0 dq 7 0 device code (-t166s4bwg) a0h v ih 00 1 device code (-b166s4bwg) v ih 10 0 1 1 0 0 0 0 0 0 0 a1h 0 1 capacitance symbol parameter test conditions pf pf unit max 8 12 typ min limits ta = 25 c, f = 1mhz, v in = v out = 0v input capacitance (address, control pins) output capacitance c in c out 1) minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is (f-v cc) +0.5v which, during transitions, may overshoot to (f-v cc) +1.5v for periods <20ns. absolute maximum ratings conditions parameter with respect to ground symbol f-v cc all input or output voltage v i1 flash v cc voltage 1) unit v v min max 4.6 -0.2 ambient temperature temperature under bias t a t bs storage temperature t stg c c c 85 -50 95 -65 125 output short circuit current i out ma 100 -0.6 4.6 -40 all currents are in rms unless otherwise noted. 1) typical values at f-vcc=3.3v, ta=25 c 2) to protect against initiation of write cycle during f-vcc power-up/ down, a write cycle is locked out for f-vcc less than v lko. if f-vcc is less than v lko, write state machine is reset to read mode. when the write state machine is in busy state, if f-vcc is less than v lko , the alteration of memory contents may occur. dc electrical characteristics (ta = -40~ 85 c, f-vcc = 2.7v ~ 3.6v, unless otherwise noted) symbol parameter max typ1) limits min test conditions unit f-v cc standby current i lo 11 output leakage current m a 0v v out f-v cc i li input leakage current m a 0v v in f-v cc 2.0 f-v cc deep powerdown current i cc3 f-v cc program current ma 35 f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp# = vih i cc4 f-v cc erase current ma 35 f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp# = vih output high voltage v v ol output low voltage v i ol = 4.0ma 0.45 (f-vcc)+0.5 v ih input high voltage v 2.0 0.8 v il input low voltage C 0.5 v oh1 i oh = C2.0ma 0.85x(f-vcc) v v oh2 i oh = C100 m a (f-vcc)C0.4 v v lko low v cc lock-out voltage 2) 1.5 2.2 v i cc5 f-v cc suspend current 200 f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp# = vih m a i sb2 5 f-v cc = 3.6v, v in =gnd or f-v cc , f-ce# = f-rp# = f-wp# = (f-v cc) 0.3v m a 0.1 15 ma i cc1 f-v cc read current for word or byte f-v cc = 3.6v, v in =v il /v ih , f-ce# = v il , f-rp#=f-oe#=v ih , i out = 0ma 8 i sb1 f-vcc = 3.6v, vin=vil/vih, f-ce# = f-rp# =f-wp# = vih m a 200 50 i cc2 15 ma f-v cc write current for word or byte f-v cc = 3.6v,v in =v il /v ih , f-ce# =f-we#= v il , f-rp#=f-oe#=v ih f-v cc = 3.6v, v in =v il /v ih , f-rp# = v il m a 15 5 i sb3 m a 0.1 i sb4 f-vcc = 3.6v, vin=gnd or f-vcc, f-rp# =gnd 0.3v 5 5mhz 4 2 1mhz note: the value of common pins to flash memory is the sum of flash memory and sram.
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 11 read-only mode ac electrical characteristics (ta = -40 ~85 c, f-vcc = 2.7v ~3.6v) write mode (f-we# control) ac electrical characteristics (ta = -40 ~85 c, f-vcc = 2.7v ~3.6v) timing measurements are made under ac waveforms for read operations. symbol parameter limits t a (ad) address access time t avqv t clz chip enable to output in low-z t elqx t a (ce) chip enable access time t elqv t a (oe) output enable access time t glqv t df(ce) chip enable high to output in high z t ehqz t rc read cycle time t avav t oh output hold from f-ce#, oe#, addresses t oh t olz t glqx output enable to output in low-z t df(oe) t ghqz output enable high to output in high z t phz f-rp# low to output high-z t plqz f-rp# recovery to f-ce# low unit ns ns ns ns ns ns ns ns ns ns ns t ps t phel f-vcc=2.7-3.6v 90 0 90 30 25 90 0 0 25 150 150 max min typ 90ns read timing parameters during command write operations mode are the same as during read-only operations mode. typical values at f-vcc=3.3v, ta=25 c symbol parameter write cycle time data hold time data set-up time address hold time address set-up time t avav t whdx t dvwh t whax t avwh t wc t dh t ds t ah t as limits 90ns 90 50 50 max min typ 0 0 unit ns ns ns ns ns write pulse width chip enable hold time chip enable set-up time write pulse width high f-rp# high recovery to write enable low block lockhold from valid srd write enable high to f-ry/by# low duration of auto-program operation duration of auto-block erase operation block lock set-up to write enable high t wlwh t wheh t elwl t whwl t phwl t qvph t whrl t whrh1 t whrh2 t phhwh t whrl t wp t ch t cs t wph t ps t bls t blh t dap t dae f-oe# hold to f-we# low t ghwl t ghwl 150 4 40 90 80 600 50 0 30 0 90 0 0 ns ns ns ns ns ns ns ms ms ns ns f-vcc=2.7-3.6v ns ns 10 30 f-oe# hold from f-we# high t whgl t oeh - t re latency between read and write ffh or 71h
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 12 erase and program performance block erase time main block write time (page mode) page write time parameter ms sec ms unit typ 4 1.0 40 max 80 1.8 600 min program suspend latency / erase suspend time program suspend latency erase suspend time parameter unit typ max 15 15 min m s m s please see page 20. vcc power up / down timing symbol unit typ 2 max min t vcs parameter f-rp# =v ih set-up time from vccmin m s please see page 13. write mode (f-ce# control) ac electrical characteristics (ta = -40 ~ 85 c, f-vcc = 2.7v ~ 3.6v) read timing parameters during command write operation mode are the same as during read-only operation mode. typical values at f-vcc=3.3v, ta=25 c symbol parameter write cycle time data hold time data set-up time address hold time address set-up time t avav t ehdx t dvwh t ehax t avwh t wc t dh t ds t ah t as limits 90ns 90 50 50 max min typ 0 0 unit ns ns ns ns ns f-ce# pulse width write enable hold time write enable set-up time f-ce# pulse width high f-rp# high recovery to write enable low block lockhold from valid srd f-ce# high to f-ry/by# low duration of auto-program operation duration of auto-block erase operation block lock set-up to write enable high t eleh t ehwh t wlel t ehel t phwl t qvph t ehrl t ehrh1 t ehrh2 t phheh t ehrl t cep t wh t ws t ceph t ps t bls t blh t dap t dae f-oe# hold to f-ce# low t ghel t ghel 150 4 40 90 80 600 60 0 30 0 90 0 90 ns ns ns ns ns ns ns ms ms ns ns f-vcc=2.7-3.6v ns ns 10 30 f-oe# hold from f-ce# high t ehgl t oeh - t re latency between read and write ffh or 71h during power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. the device must be protected against initiation of write cycle for memory contents during power up/down. the delay time of min.2 m sec is always required before read operation or write operation is initiated from the time f-vcc reaches f-vccmin during power up/down. by holding f-rp# vil, the contents of memory is protected during f-vcc power up/down. during power up, f-rp# must be held vil for min.2 m s from the time f-vcc reaches f-vccmin. during power down, f-rp# must be held vil until vcc reaches gnd. f-rp# doesn't have latch mode ,therefore f-rp# must be held vih during read operation or erase/program operation.
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 13 3.3v gnd f-v cc vcc power up / down timing v ih v il f-rp# read /write inhibit t vcs v ih v il f-ce# v ih v il f-we# t ps t ps read /write inhibit read /write inhibit test conditions for ac characteristics input voltage : v il = 0v, v ih = 3.0v input rise and fall times : 5ns reference voltage at timing measurement : 1.5v output load : 1ttl gate + cl(30pf) or ac waveforms for read operation and test conditions output valid high-z t df(oe) t rc v ih v il v ih v il v ih v il v ih v il v oh v ol addresses f-ce# f-oe# f-we# data address valid t oh t olz t a (ce) t oeh t clz t a (ad) t a (oe) high-z dut 3.3k w 1n914 1.3v c l =30pf v ih v il f-rp# t ps t df(ce) t phz t re ac waveforms for write ffh or 71h and read operation output valid high-z t df(oe) t rc v ih v il v ih v il v ih v il v ih v il v oh v ol addresses f-ce# f-oe# f-we# data address valid t oh t olz t a (ce) t re t clz t a (ad) t a (oe) high-z v ih v il f-rp# t ps t df(ce) t phz valid ffh or 71h in the case of use f-ce# is low fixed, it is allowed to define a timming specification of tre from rising edge of f-we# to falling edge of f-oe#, and valid data is read after spec of tre+ta(ce). (this is only for ffh,71h program and read)
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 14 ac waveforms for page program operation (f-we# control) 41h din t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il address valid f-ce# f-oe# f-we# data f-ry/by# t ah v ih v oh v ol v il t as din srd din v ih v il t oeh t dap t whrl program read status register write read array command ffh 7fh 01h~7eh 00h t a(ce) t a(oe) v il v ih v il t blh t bls t ps v ih f-rp# bank address valid the other bank address valid valid dout t oeh t ghwl t a(oe) t a(ce) valid f-a19~f-a17, a16~a7 a6 ~a0 f-wp# bank address valid ac waveforms for page program operation (f-ce# control) 41h din t ceph t cep t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il address valid f-ce# f-oe# f-we# data t ah v ih v il t as din srd din v ih v il t oeh t dap program read status register write read array command ffh 7fh 01h~7eh 00h t a(ce) t a(oe) bank address valid valid valid valid dout t a(ce) t oeh t ghel t a(oe) the other bank address f-ry/by# v oh v ol t ehrl t ps v ih v il f-rp# v ih v il f-wp# t blh t bls f-a19~f-a17, a16~a7 a6 ~a0 bank address valid
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 15 ac waveforms for word program operation (f-we# control) (to only bank(i)) write read array command read status register v ih v il address valid program v ih v il v ih v il v ih v ih f-ce# f-oe# f-we# data f-ry/by# v il v ih v il v ih v il f-rp# v ih v il f-wp# v il 40h din t cs t ch t wph t wp t ds t ps t dap t whrl t oeh t a(ce) t a(oe) t blh t dh srd ffh t ah t as t wc t bls bank(i) address valid bank address valid ac waveforms for word program operation (f-ce# control) (to only bank(i)) write read array command read status register v ih v il addresses address valid program v ih v il v ih v il v ih v ih f-ce# f-oe# f-we# data f-ry/by# v il v ih v il v ih v il f-rp# v ih v il v il 40h din t ws t wh t cep t ds t ps t dap t ehrl t oeh t a(ce) t a(oe) t blh t dh srd ffh t ah t as t wc t bls bank(i) address valid f-wp# bank address valid addresses
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 16 ac waveforms for erase operations (f-we# control ) ac waveforms for erase operations (f-ce# control) 20h d0h t ceph t cep t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il f-ry/by# t ah v ih v oh v ol v il addresses t as ffh srd t oeh t dae t ehrl address valid erase read status register write read array command f-ce# f-oe# f-we# data t a(oe) t a(ce) bank address valid v il v ih v il t ps v ih f-rp# f-wp# t blh t bls bank address valid 20h d0h t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il f-ry/by# t ah v ih v oh v ol v il addresses t as ffh srd t oeh t dae t whrl address valid erase read status register write read array command f-ce# f-oe# f-we# data t a(oe) t a(ce) bank address valid v il v ih v il t ps v ih f-rp# t bls t blh f-wp# bank address valid
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 17 ac waveforms for page program operation with bgo (f-we# control) array read from the other bank with bgo v ih v il v ih v il v ih v il v ih v ih address valid f-ce# f-oe# f-we# data f-ry/by# v ih v il v il v ih v il 7fh 01h~7eh 00h v il 41h din dout din din srd valid valid valid valid t wc t as t ah t cs t ch t wph t wp t ds t dh t whrl t a(ce) t a(oe) t oeh dout program data to one bank change bank address f-a19~f-a17, a16~a7 a6 ~a0 bank address valid ac waveforms for page program operation with bgo (f-ce# control) array read from the other bank with bgo v ih v il v ih v il v ih v il v ih v ih address valid f-ce# f-oe# f-we# data f-ry/by# v ih v il v il v ih v il 7fh 01h~7eh 00h v il 41h din dout din din srd valid valid valid valid t wc t as t ah t ws t ch t ceph t cep t ds t dh t ehrl t a(ce) t a(oe) t oeh dout program data to one bank change bank address f-a19~f-a17, a16~a7 a6 ~a0 bank address valid ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 18 ac waveforms for word program operation with bgo (f-we# control) array read from bank(ii) with bgo v ih v il v ih v il v ih v il v ih v ih address valid f-ce# f-oe# f-we# data f-ry/by# v ih v il v il v ih v il v il 40h din srd dout valid valid valid valid t wc t as t ah t cs t ch t wph t wp t ds t dh t whrl t a(ce) t a(oe) t oeh dout program data to bank(i) valid read status register change bank address f-a19~f-a17, a16~a7 a6 ~a0 bank address valid ac waveforms for word program operation with bgo (f-ce# control) change bank address array read from bank(ii) with bgo v ih v il v ih v il v ih v il v ih v ih f-ce# f-oe# f-we# data f-ry/by# v ih v il v il v ih v il v il 40h din srd dout valid valid valid valid t wc t as t ws t ch t ceph t cep t ds t dh t ehrl t a(ce) t a(oe) t oeh dout program data to bank(i) valid address valid read status register a6 ~a0 bank address valid f-a19~f-a17, a16~a7
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 19 ac waveforms for block erase operation with bgo (f-we# control) array read from the other bank with bgo v ih v il v ih v il v ih v il v ih v ih addresses address valid f-ce# f-oe# f-we# data f-ry/by# v il v ih v il v il 20h d0h srd dout valid valid t wc t as t ah t cs t ch t wph t wp t ds t dh t whrl t a(ce) t a(oe) t oeh dout block erase in one bank read status register change bank address bank address valid ac waveforms for block erase operation with bgo (f-ce# control) v ih v il v ih v il v ih v il v ih v ih f-ce# f-oe# f-we# data f-ry/by# v il v ih v il v il 20h d0h srd dout valid valid t wc t as t ws t ch t ceph t cep t ds t dh t ehrl t a(ce) t a(oe) t oeh dout address valid t ah read data from the other bank with bgo addresses block erase in one bank read status register change bank address bank address valid
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 20 ac waveforms for suspend operation (f-ce# control ) b0h v ih v il v ih v il v ih v il v ih v il f-ry/by# v ih v oh v ol v il addresses t as t oeh program suspend latency t cep bank address valid read status register f-ce# f-oe# f-we# data t a(oe) t a(ce) bank address valid v il v ih v il v ih f-rp# t bls valid srd t blh t ah t ws t wh f-wp# s.r.6,7=1 ac waveforms for suspend operation (f-we# control ) b0h t wp t cs t ch v ih v il v ih v il v ih v il v ih v il f-ry/by# v ih v oh v ol v il addresses t as t oeh bank address valid read status register f-ce# f-oe# f-we# data t a(oe) t a(ce) bank address valid v il v ih v il v ih f-rp# t bls t blh t ah valid srd program suspend latency f-wp# s.r.6,7=1
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 21 full status check procedure sr.5 = 0 ? sr.4 = 0 ? sr.4 =1 and sr.5 =1 ? successful (block erase, program) yes yes yes no status register read command sequence error no block erase error no program error (block) write 77h write d0h block address lock bit program flow chart sr.4 = 0 ? lock bit program successful yes yes no no start lock bit program failed sr.7 = 1 ? sr.3 = 0 ? yes no program error (page, lock bit) page program flow chart start write 41h full status check if desired page program completed yes n = 0 n = n+1 write address n, data n yes sr.7 = 1 ? n = ffh ? or n = 7fh ? no write b0h ? yes no suspend loop write d0h yes no status register read word program flow chart start write 40h full status check if desired word program completed yes write address , data sr.7 = 1 ? write b0h ? yes no suspend loop write d0h yes no status register read * word program is admitted to only bank(i).
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 22 suspend / resume flow chart start write b0h operation resumed sr.6 =1? yes no write ffh read array data done reading ? no yes write d0h suspend resume block erase flow chart start write 20h write d0h block address full status check if desired yes sr.7 = 1 ? write b0h ? yes no suspend loop write d0h yes no status register read block erase completed status register read sr.7 = 1? yes no program / erase completed * the bank address is required when writing this command. also, there is no need to suspend the erase or program operation when reading data from the other bank. please use bgo function. single data load to page buffer start write 74h full status check if desired page buffer to flash completed write address , data write b0h ? yes no suspend loop write d0h yes no status register read write 0eh write d0h page address sr.7 = 1 ? yes done loading? no single data load to page buffer completed page buffer to flash start clear page buffer start write 55h write d0h page buffer clear completed
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 23 operation status and effective command page program setup lock bit program setup block erase setup setup state read/standby state other erase & verify read status register b0h d0h b0h d0h 50h 41h 77h 20h a7h suspend state read array read status register ffh 70h 70h read status register read device identifier read lock status ffh 70h 90h 70h 90h ffh ffh 71h 70h 71h 90h read array other other d0h d0h d0h wdi i=0-127 erase all unlocked blocks setup program & verify read status register 71h clear status register ready change bank address read array (from the other bank) change bank address read state with bgo 40h word program setup wd 0eh d0h single data load to page buffer setup 74h wd other page buffer to flash setup internal state clear page buffer setup 55h d0h read array (from the other bank) change bank address
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 24 when setting s-lb# at the high level and other pins are in an active stage, upper-byte are in selectable mode in which both reading and writing are enabled, and lower-byte are in non-selectable mode. and when setting s-ub# at a high level and other pins are in an active stage, lower-byte are in a selectable mode and upper-byte are in a non-selectable mode. when setting s-lb# and s-ub# at a high level or s-ce1# at high level or s-ce2 at a low level, the chips are in a non- selectable mode in which both reading and writing are disabled. in this mode, the output stage is in a high- impedance state, allowing or-tie with other chips and memory expansion by s-lb#,s-ub# and s-ce1#,s-ce2. the power supply current is reduced as low as 0.3 m a(25 c,typical), and the memory data can be held at +2v powersupply, enabling battery back-up operation during power failure or power-down operation in the non-selected mode. the sram of m6mgb/t166s4bwg is organized as 262,144-word by 16-bit. these devices operate on a single +2.7~3.6v powersupply, and are directly ttl compatible to both input and output. its fully static circuit needs no clocks and no refresh, and makes it useful. the operation mode are determined by a combination of the device control inputs , s-lb#,s-ub#,s-ce1#,s-ce2, s-we# and s-oe#. each mode is summarized in the function table. a write operation is executed whenever the low level s-we# overlaps with the low level s-lb# and/or s-ub# and the low level s-ce1#the high level s-ce2. the address a0~a16,sa-17 must be set up before the write cycle and must be stable during the entire cycle. a read operation is executed by setting s-we# at a high level and s-oe# at a low level while s-lb# and/or s-ub# and s-ce1# and s-ce2 are in an active state(s-ce1#=l,s-ce2=h). function table mode s-we# high-z s-oe# dq0~7 non selection high-z s-ub# icc standby dq8~15 s-lb# s-ce2 s-ce1# l h h x high-z din read dout high-z write active active active l l l l high-z din read dout high-z write active active active l l l l l l l h x h h h h h h h h h x x x h l l l h h h l l l x x x h h h h l l l l l l x x x x h l h l h h l h h x x x x l x h x h l x l h non selection non selection non selection read write high-z high-z high-z high-z high-z high-z high-z high-z high-z high-z din dout high-z din dout high-z standby standby standby active active active 2. sram
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg absolute maximum ratings supply voltage input voltage output voltage power dissipation operating temperature storage temperature v mw conditions ta=25 c 700 - 40 ~ +85 c - 65 ~ +150 c ratings s-v cc v i v o p d t a t stg -0.5 * ~ +4.6 -0.5 * ~ (s-vcc) + 0.5 0 ~ s-vcc symbol parameter units i-version with respect to gnd with respect to gnd with respect to gnd * -3.0v in case of ac (pulse width 30ns) 25 pf 10 10 v i =gnd, v i =25mvrms, f=1mhz v o = gnd,v o =25mvrms, f=1mhz c i c o (s-vcc=2.7 ~ 3.6v, unless otherwise noted) symbol parameter conditions limits max typ min units input capacitance output capacitance capacitance note: the value of common pins to sram is the sum of flash memory and sram. c c < = dc electrical characteristics ( s-vcc=2.7 ~ 3.6v, unless otherwise noted) * -3.0v in case of ac (pulse width 30ns) < = note 1: direction for current flowing into ic is indicated as positive (no mark) note 2: typical value is for s-vcc=3.0v and ta=25 c symbol parameter limits conditions units m a ma ma v icc 1 icc 2 icc 4 v ih v il i o icc 3 v oh1 i oh = -0.5ma v oh2 i oh = -0.05ma v ol i ol =2ma i i v i =0 ~ s-vcc s-lb# and s-ub#=v ih or s-ce1#=v ih or s-ce2=v ih or s-oe#=v ih , v i/o =0 ~ s-vcc (s-vcc)+0.3v 0.6 2.2 -0.3 * 2.4 1.0 0.4 1 70 50 (s-vcc)-0.5v 1 15 max typ min f= 10mhz f= 1mhz - - - - - f= 10mhz f= 1mhz 7 70 50 15 7 - high-level input voltage low-level input voltage high-level output voltage 1 high-level output voltage 2 low-level output voltage input leakage current output leakage current active supply current ( ac,mos level ) ( ac,ttl level ) active supply current stand by supply current ( ac,mos level ) ( ac,ttl level ) stand by supply current other inputs=0~s-vcc s-ce2 0.2v - 40 ~ +25 c m a 20 +25 ~ +40 c - - - 1 3.6 - - 40 +70 ~ +85 c +40 ~ +70 c - 0.3 1.2 s-lb# and s-ub#=vil,s-ce1#=vil, s-ce2=vih other inputs=vih or vil output-open(duty 100%) + - + - < = s-lb# and s-ub# 0.2v,s-ce1# 0.2v, s-ce2 (s-vcc)-0.2v other inputs 0.2v or (s-vcc)-0.2v output-open(duty 100%) < = < = < = > = > = 1)s-ce2=vil,other inputs=0 - s-vcc 2)s-ce1#=vih, s-ce2=vih or vil,other inputs=0 - s-vcc 3)s-lb# and s-ub#=vih , s-ce1#=vih or vil s-ce2=vih or vil, other inputs=0 - s-vcc
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 26 ac electrical characteristics (s-vcc=2.7 ~ 3.6v, unless otherwise noted) (1) test conditions input rise time and fall time reference level output loads 2.7v~3.6v v ih =2.4v, v il =0.4v v oh =v ol =1.5v transition is measured 500mv from steady state voltage.(for t en ,t dis ) 5ns fig.1,cl=30pf cl=5pf (for ten,tdis) supply voltage input pulse 1ttl cl dq fig.1 output load including scope and jig capacitance (3) write cycle t su (a-wh) t cw t w (w) t su (a) t su (ce1) t su (d) t h (d) t rec (w) t dis (w) t dis (oe) t en (w) t en (oe) chip select 1 setup time ns 85 ns ns ns ns ns ns ns ns symbol parameter limits units max min write cycle time write pulse width address setup time address setup time with respect to s-we# lower byte control setup time data setup time data hold time write recovery time output disable time from s-oe# high output enable time from s-we# high output disable time from s-we# low output enable time from s-oe# low ns ns ns ns ns 50 0 70 30 30 5 5 t su (lb) t su (ub) upper byte control setup time 70 70 70 35 0 0 sram t su (ce2) chip select 2 setup time ns 70 (2) read cycle output disable time after s-ce1# high t cr ns t a (ce1) t a (oe) t dis (ce1) t dis (oe) t en (ce1) t en (oe) t v (a) t a (a) 85 10 45 sram ns ns ns ns ns ns ns ns symbol parameter limits units max min read cycle time address access time chip select 1 access time output enable access time data valid time after address t a (lb) t a (ub) lower byte control access time upper byte control access time t dis (lb) t dis (ub) output disable time after s-lb# high output disable time after s-ub# high output disable time after s-oe high t dis (lb) t dis (ub) output enable time after s-lb# low output enable time after s-ub# low output enable time after s-ce1# low output enable time after s-oe low ns ns ns ns ns ns 85 85 85 85 30 30 30 30 10 10 5 10 t a (ce2) ns chip select 2 access time 85 t en (ce2) 10 output enable time after s-ce2 high ns output disable time after s-ce2 low t dis (ce2) ns 30 + -
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 27 (4)timing diagrams t a (a) t a (lb) t v (a) t dis (lb) or t dis (ub) t a (oe) t en (oe) t dis (oe) t cr t en (ce1) s-we# = "h" level dq 0~15 a 0~16, s-a 17 s-oe# read cycle (note3) (note3) (note3) (note3) valid data t a (ce1) t dis (ce1) s-ce1# (note3) (note3) t a (ub) or t en (ub) t en (lb) t a (ce2) t dis (ce2) s-ce2 (note3) (note3) t en (ce2) s-ce2 (note3) (note3) t su (ce2) t en (w) t h (d) t su (d) dq 0~15 t su (lb) or t su (ub) t en (oe) t dis (oe) t w (w) t rec (w) t su (a) t dis (w) t cw s-oe# s-we# write cycle (s-we# control mode) data in stable (note3) (note3) t su (a-wh) s-ce1# (note3) (note3) t su (ce1) s-lb#, s-ub# a 0~16, s-a 17 s-lb#, s-ub#
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 28 write cycle (s-lb#,s-ub# control mode) note 3: hatching indicates the state is "don't care". note 4: a write occurs during s-ce1# low, s-ce2 high overlaps s-lb# and/or s-ub# low and w low. note 6: don't apply inverted phase signal externally when dq pin is in output mode. note 5: when the falling edge of s-we# is simultaneously or prior to the falling edge of s-lb# and/or s-ub# or the falling edge of s-ce1# or rising edge of s-ce2, the outputs are maintained in the high impedance state. t h (d) t su (d) dq 0~15 t su (lb) or t su (ub) t rec (w) t su (a) t cw a 0~16 , s-a 17 s-we# data in stable (note3) (note3) (note4) (note5) (note3) (note3) s-ce1# s-lb#, s-ub# (note3) (note3) s-ce2
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg 29 write cycle (s-ce1# control mode) t h (d) t su (d) dq 0~15 t su (ce1) t rec (w) t su (a) t cw a 0~16 , s-a 17 s-we# s-ce1# data in stable (note3) (note3) (note4) (note5) (note3) (note3) s-lb#, s-ub# (note3) (note3) s-ce2 t h (d) t su (d) dq 0~15 t su (ce2) t rec (w) t su (a) t cw a 0~16 , s-a 17 s-we# s-ce1# write cycle (s-ce2 control mode) data in stable (note3) (note3) (note4) (note5) (note3) (note3) s-lb#, s-ub# (note3) (note3) s-ce2
nov. 1999 , rev.3.2 mitsubishi lsis 16,777,216-bit (1,048,576 -word by 16-bit ) cmos 3.3v-only flash memory & 4,194,304-bit (262,144-word by 16-bit) cmos sram stacked-csp (chip scale package) m6mgb/t166s4bwg power down characteristics t su (pd) t rec (pd) ns ms (2) timing requiremints symbol parameter test conditions limits min typ max units power down set up time power down recovery time 0 5 30 (1) electrical characteristics v v 2.0 s-vcc (pd) v i (s-bc) symbol parameter test conditions limits min typ max units power down supply voltage byte control input s-lb#,s-ub# 2.0 typical value is for ta=25 c icc (pd) -i power down supply current (3) timing diagram 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) s-vcc s-lb#, s-ub# s-lb#,s-ub# control mode 2.2v t su (pd) 2.7v 2.7v 2.2v t rec (pd) s-vcc s-ce1# s-ce1# control mode s-ce1# (s-vcc) - 0.2v s-vcc s-ce2 control mode 0.2v t su (pd) 2.7v 2.7v 0.2v t rec (pd) s-ce2 s-ce2 0.2v v v 2.0 v i (s-ce1#) v i (s-ce2) chip select input s-ce1# chip select input s-ce2 0.2 s-vcc=3.0v s-ce2 0.2v other inputs=0~3v < = < = > = s-lb#,s-ub# (s-vcc) - 0.2v > = m a 15 +25 ~ +40 c - - - 1 3 - - 30 +70 ~ +85 c +40 ~ +70 c - 0.3 1 - 40 ~ +25 c

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